The present invention relates to a method for isolating faulty digital logic gates in a logic circuit.
Manufacturers of digital computer systems typically sell diagnostic software with their systems to allow their customers to locate faulty parts for servicing. Prior methods for isolating faults utilized simulators to generate fault dictionaries by inserting faults into a simulation of the circuit to be tested and simulating both the faulty and the normally operating circuits until their outputs differ. The simulated normal output of each system component is then compared with the simulated faulted output and the responses of the faulty and good circuit are tabulated into a fault dictionary. A fault could potentially occur at the point of signal discrepancy or at any circuit element feeding into that point. This method required long run times for processing the simulation program because of the numerous fault possibilities to be tested. The run time was approximately equal to the number of the logic gates to the power of 3. With very large networks, the simulations could also exceed the memory capacity of the computer.
The method of fault isolation described above was also susceptible to problems due to uninitialized logic. Uninitialized logic occurs when random information is stored in logic gates after the system is powered up but before the system begins to execute programs. The result of having uninitialized logic in the circuit is that it can occur in parts of the circuit not yet tested and can feed back ambiguous information resulting in an erroneous fault isolation.
One prior art method for dealing with this uninitialized logic problem employed the addition of extra scan logic hardware into the circuit design. The extra hardware was utilized to allow the programmer to set the logic state of every circuit element in the system prior to initiating fault isolation. However, the use of scan logic hardware for fault isolation increases the cost of the system without any increase in system performance.